10-16 Status Structure Model 6487 Reference Manual
Event registers
As Figure 10-1 shows, each status register set has an event register. When an event occurs,
the appropriate event register bit sets to 1. The bit remains latched to 1 until the register is
reset. Reading an event register clears the bits of that register. *CLS resets all four event
registers.
The commands to read the event registers are listed in Table 10-5. For details on reading
registers, see “Reading registers,” page 10-6.
Event enable registers
As Figure 10-1 shows, each status register set has an enable register. Each event register
bit is logically ANDed (&) to a corresponding enable bit of an enable register. Therefore,
when an event bit is set and the corresponding enable bit is set (as programmed by the
user), the output (summary) of the register will set to 1, which in turn sets the summary bit
of the status byte register.
The commands to program and read the event enable registers are listed in Table 10-6. For
details on programming and reading registers, see “Programming enable registers,”
page 10-5 and “Reading registers,” page 10-6.
klqb The bits of any enable register can be reset to 0 by sending the
0 parameter value with the appropriate enable command
(i.e. STATus:OPERation:ENABle 0).
Table 10-5
Common and SCPI commands — event registers
Command Description
*ESR?
STATus
:OPERation:[:EVENt]?
:MEASurement:[:EVENt]?
:QUEStionable:[:EVENt]?
Read standard event status register.
STATus subsystem:
Read operation event register.
Read measurement event register.
Read questionable event register.
Note: Power-up and *CLS resets all bits of all event registers to 0. STATus:PRESet has no effect.
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