Marantz SR9600 - Page 129

181
QF61 : SAA7115HL/V1/G
analog
dual
ADC
Line
FIFO
buffer
FIR - Prefilter
Horizontal
Scaling
RT out
IIC
video
FIFO
32
MUX
8(16)
to
programming
Register
array
A / B
MUX
Reg.
general purpose
VBI data slicer
event controller
video / text
arbiter
X port I/O formatting
frame locked
PLL
eXpansion port pin mapping
Image port pin mapping
digital
decoder
boundary
test
scan
XTRI
IPD[7:0]
IGPV
XRDY
LLC
LLC2
RTCO
RTS0
RTS1
HPD[7:0]
TEST1
TEST2
TEST5
TEST4
TEST3
AI11
AI12
AI21
AI22
AI23
AI24
TRSTN
TCK
TMS
TDI
TDO
AXMCLK
ALRCLK
ASCLK
*)
AMCLK
*)
IGPH
IDQ
TEST0
AOUT
XTALO
XTALI
XTOUT
CE
RESON
clock generation and
power on control
The Pins RTCO and ALRCLK
definition of the crystal osc.
Note:
SCL
SDA
Prescaler
Fine
(Phase)
text
FIFO
of the IIC interface and the
are used for configuration
frequency at RESET
Block diagram SAA7115
with
adaptive
comb
filter
I/O control
(pin strapping)
and
scaler BCS
Vertical
Scaling
XCLK
XDQ
XPD[7:0]
XRH
*)
XRV
*)
IGP1
IGP0
ITRI
ITRDY
ICLK
VDDI
VDDE
VDDA
VSSI
VSSE
VSSA
AGND
30
27 4
7
6
20
18 16
14
12
10
22 19
AI1D
AI2D
13
28
29
36
34
35
94
95
81,82,
92
91
96
8084-87,
89,90
64-67, 69-72
32
31
79
78
77
74
73 44
53
46
48
52
47
42
54-57, 59-62
45
49
97
98
99
3
2
37
40
39
41
33,43, 58,68, 83,93
1,25, 51,75
11,17, 23
38,63, 88
26,50, 76,100
9,15, 24
VXDD
VXSS
8
5
Fig.1 SAA7115 Block Diagram
PLL2
audio clock
CGC2
audio clock
generation
puls generator