Mitsubishi Electric R64MTCPU - Page 79

2 MOTION DEDICATED PLC INSTRUCTION
2.2 Motion Dedicated PLC Instruction
77
2
Processing details
■Controls
• For a Multiple CPU system configuration, the bit device specified with (D1) of the target CPU (n1) turns ON or OFF with the
bit operation of (n2).
If reading a bit device of the target CPU, use the M(P).DDRD/D(P).DDRD instructions. Refer to the following
for details on the M(P).DDRD/D(P).DDRD instructions.
MELSEC iQ-R Programming Manual (Instructions, Standard Functions/Function Blocks)
■Operation
Outline operation between CPUs at the MP.BITWR and DP.BITWR instruction execution is shown below.
• MP.BITWR instruction
• DP.BITWR instruction
*1 Set in [System Parameter]  [Multiple CPU settings] in GX Works3
Sequence program
MP.BITWR instruction
ON
MP.BITWR
execution
Request data set
Target CPU MP.BITWR
accept processing
END END
Complete device (D2+0)
ON
Status display device (D2+1)
at the completion
CPU dedicated transmission
(Non-fixed cycle)
END
1 scan
Transfer
MP.BITWR accept
processing
Response
data set
ON: Abnormal completion only
Transfer
ON
DP.BITWR
execution
Request data set
END END
ON
END
1 scan
Transfer Transfer
DP.BITWR accept
processing
Response
data set
ON: Abnormal
completion only
Sequence program
DP.BITWR instruction
Target CPU DP.BITWR
accept processing
Complete device (D2+0)
Status display device (D2+1)
at the completion
CPU dedicated transmission
(Fixed cycle)
Communication
cycle
*1