Motorola MVME2400 Series - PPC Bus Latency; Table 3-5. Ppc60 X Originated Latency Matrix

Block Diagram
http://www.motorola.com/computer/literature 3-9
3
PPC Bus Latency
The following tables list the latency of PPC originated transactions and the
bandwidth of originated transactions for five different clock ratios: 5:2,
3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio:
Table 3-5. PPC60x Originated Latency Matrix
Transaction
32-bit PCI 64-bit PCI
Clock
Ratio
Beat
1
Beat
2
Beat
3
Beat
4
Total
Beat
1
Beat
2
Beat
3
Beat
4
Total
Burst Read401114329111325:2
Burst Write5111851118
Single Read22---22-----
Single Write5---5-----
Burst Read261112920111233:2
Burst Write5111851118
Single Read16---16-----
Single Write5---5-----
Burst Read451114833111363:1
Burst Write5111851118
Single Read24---24-----
Single Write5---5-----
Burst Read331113625111282:1
Burst Write5111851118
Single Read19---19-----
Single Write5---5-----
Burst Read201112316111191:1
Burst Write5111851118
Single Read13---13-----
Single Write5---5-----