NXP Semiconductors QorIQ T1040 - 3.2.1 Chip ID1 register (CHIPID1); 3.2.2 Chip ID2 register (CHIPID2); 3.2.3 Hardware version register (HWVER)

3.2.1 Chip ID1 register (CHIPID1 )
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7
Read CHIPID1
Write
Reset
0 1 0 1 0 1 0 1
CHIPID1 field descriptions
Field Description
0–7
CHIPID1
0x55, Identification of the CPLD image.
3.2.2 Chip ID2 register (CHIPID2)
Address: 0h base + 1h offset = 1h
Bit 0 1 2 3 4 5 6 7
Read CHIPID2
Write
Reset
1 0 1 0 1 0 1 0
CHIPID2 field descriptions
Field Description
0–7
CHIPID2
0xaa, Identification of the CPLD image.
3.2.3 Hardware version register (HWVER)
Address: 0h base + 2h offset = 2h
Bit 0 1 2 3 4 5 6 7
Read HW_VER
Write
Reset
n* n* n* n* n* n* n* n*
* Notes:
HW_VER field: n=Depends on PLD image revision•
Chapter 3 CPLD specification
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 45