NXP Semiconductors QorIQ T1040 - 2.4 Reset; 2.5 DDR

2.4 Reset
The CPLD manages the reset signals to and from the T1040 processor and the other
devices on the T1040RDB board. The figure below shows an overview of the reset
architecture.
ATX PS
PWR_GODD
GND
Push-Button
MAX811S
(Power-on RST)
PON_RST_N
COP_SRST_N
COP_ITF
T1040
HESET_REQ_N
HRSET_N
PORESET_N
Reset
source
select
RST_CTL
DDR_RSTN
TDMR_RST
TDMR
SLOT
QSG2_RST_N
QSGMII
GE PHY
QSG1_RST_N
EC1_RST_N
RGMII
GE PHY1
Soft reset register
RSTCON1 & RSTCON2
SW_RST
7
CPLD
COP_HRST_N
6
5
4
3
2
1
0
EC2_RST_N
RGMII
GE PHY2
DDR3/
DDR3L
CORE_power
(IR36021)
VCORE_PGD
NOR
FLASH
PEX SLOT
MINI PEX
SLOT
MINI PEX
SLOT
SGMII
GE PHY
QSGMII
GE PHY
MPEX2_RST
PEX_RST
MPEX1_RST
NOR_RSTN
SG_RST_N
Figure 2-3. CPLD logical
2.5 DDR
The T1040RDB supports high-speed DRAM with an unbuffered DDR3L (240pin) socket
(UDIMM), featuring single-, dual-, and quad-rank support. The memory interface
includes all the necessary termination and I/O power, and is routed so as to achieve
maximum performance of the memory bus, as shown in the below figure.
Reset
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
18 Freescale Semiconductor, Inc.