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NXP Semiconductors QorIQ T1040 - 1.3 Silicon features; 1.4 Board features

NXP Semiconductors QorIQ T1040
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1.3 Silicon features
NOTE
For a description of the features of the T1040 SoC, see QorIQ
T1040 Reference Manual (T1040RM).
1.4 Board features
The features of the T1040RDB-PA board are as follows:
Eight lanes of SerDes connections with support for:
PCIe that supports Gen 1 and Gen 2
SGMII
QSGMII
SATA 2.0
DDR controller
Supports data rates up to 1600 MHz
Supports one DDR3L DIMM of single-, dual-, or quad-rank type
DDR power supply (1.35 V) with automatic tracking of VTT
IFC
NAND flash: 8-bit, async, 1 GB
NOR: 16-bit, non-multiplexed, 128 MB, support of eight virtual banks
Ethernet
Two onboard RGMII 10/100/1G Ethernet ports, PHY #0 remains powered up
during deep-sleep
One onboard SGMII 10/100/1G Ethernet Port
Two onboard QSGMII 10/100/1G PHYs connecting to 8 GE ports
CPLD
Manages system power and reset sequencing
Manages DUT, board, clock configuration
Reset and interrupt monitor and control
General fault monitoring and logging
Sleep mode control
Clocks
SYSCLK at 100 MHz
DDRCLK at 66.66 MHz
USBCLK at 24 MHz
Single Oscillator Source reference clocking at 100 MHz
Power Supplies
Chapter 1 Overview
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 9

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