NXP Semiconductors QorIQ T1040 - 3.2.6 Reset control register (RSTCON2)

RSTCON1 field descriptions (continued)
Field Description
4
SG_RST
0: No reset occurs.
1: Writing logic 1 produces SGMII PHY(RTL82111DN) reset# signal, this bit can auto clear.
5
QSG1_RST
0: No reset occurs.
1: Writing logic 1 produces QSGMII PHY(VSC8514) reset# signal, this bit can auto clear.
6
QSG2_RST
0: No reset occurs.
1: Writing logic 1 produces 10G PHY(CS4315) reset# signal, this bit can auto clear.
7
XG_RST
0: No reset occurs
1: Writing logic 1 produces 10G PHY (CS4315)reset# signal, this bit can auto clear.(Bit 7 needs to go)
3.2.6 Reset control register (RSTCON2)
Address: 0h base + 11h offset = 11h
Bit 0 1 2 3 4 5 6 7
Read
Reserved
TDMR_RST PEX_RST
MPEX1_
RST
MPEX2_
RST
Write
w1c
w1c
w1c w1c
Reset
0 0 0 0 0 0 0 0
RSTCON2 field descriptions
Field Description
0–3
-
This field is reserved.
4
TDMR_RST
0: No reset occurs.
1: Writing logic 1 produces TDM riser card reset# signal, this bit can auto clear.
5
PEX_RST
0: No reset occurs.
1: Writing logic 1 produces PCIe x4 slot reset# signal, this bit can auto clear.
6
MPEX1_RST
0: No reset occurs.
1: Writing logic 1 produces miniPCIe card1 reset# signal, this bit can auto clear.
7
MPEX2_RST
0: No reset occurs
1: Writing logic 1 produces miniPCIe card2 reset# signal, this bit can auto clear.
Chapter 3 CPLD specification
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 47