NXP Semiconductors QorIQ T1040 - 3.2.11 SFP+ control and status register (SFPCSR); 3.2.12 Miscellaneous control and status register (MISCCSR)

3.2.11 SFP+ control and status register (SFPCSR )
Address: 0h base + 16h offset = 16h
Bit 0 1 2 3 4 5 6 7
Read
Reserved
Write
Reset
0 0 0 0 0 0 0 0
SFPCSR field descriptions
Field Description
0–7
-
This field is reserved.
3.2.12 Miscellaneous control and status register (MISCCSR )
Address: 0h base + 17h offset = 17h
Bit 0 1 2 3 4 5 6 7
Read
SPI_CS3_
SEL
SLEEP_EN REQ_MD
TDMR_PRS PEX_PRS T2081_DET
TEST_SEL_
N
Write
Reset
0 0 1 1 0 n n n
MISCCSR field descriptions
Field Description
0
SPI_CS3_SEL
0: SPI_CS3 select TDMR SPI CS0
1: SPI_CS3 select TDMR SPI CS1
1
SLEEP_EN
Before entering deep sleep mode, set ‘1’ to this bit, after exiting deep sleep mode, set ‘0’ to this bit
0 Normal operation
1 Deep sleep enable bit
2–3
REQ_MD
00 No reset occurs when HRESET_REQ triggered.
01 HRESET occurs when HRESET_REQ triggered.
10 Reserved
11 PORESET occurs when HRESET_REQ triggered.
4
TDMR_PRS
0: TDM riser card not present
1: TDM riser card present
5
PEX_PRS
0 PCIe card not present in x4 slot.
1 PCIe card present in x4 slot.
6
T2081_DET
0: T1040 on board
1: T2081 on board
7
TEST_SEL_N
0: TEST_SEL_N pin status is 0
1: TEST_SEL_N pin status is 1
Chapter 3 CPLD specification
QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015
Freescale Semiconductor, Inc. 51