Between the DRAM (IC503), Gate Array IC (IC520) signal lines are controlled by voltages of 5V (H)
or 0V (L).
Digital Block Diagram
You also need to check the signal lines listed here [List 1] when the unit fails to boot up the
system. Those signal lines should remain normal. Other signal lines are not directly related to
that failure even if they have faults or troubles.
As long as these signals remain normal, once the power is turned on, each IC can repeatedly
output 3.3V (H) and 0V (L) (IC503 and IC520 output 5V(H) and 0V(L)). The following shows NG and
normal wave patterns.
NG Wave pattern (Refer to NG EXAMPLE)
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