Quectel 5G Series - Page 23

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 22 / 85
(U)SIM2 card
1.8/3.0 V
49
PCIE_RX_P
AI
PCIe receive (+)
50
PCIE_RST_N
DI, OD
PCIe reset.
Active LOW
51
GND
Ground
52
PCIE_CLKREQ_N
DO, OD
PCIe clock request.
Active LOW.
53
PCIE_REFCLK_M
AI, AO
PCIe reference clock (-)
54
PCIE_WAKE_N
DO, OD
PCIe wake up.
Active LOW
55
PCIE_REFCLK_P
AI, AO
PCIe reference clock
(+)
56
RFFE_CLK
2)
DO, PD
Used for external MIPI
IC control
1.8 V
57
GND
Ground
58
RFFE_DATA
2)
DO, PD
Used for external MIPI
IC control
1.8 V
59
LAA_TX_EN*
DO
Notification from SDR to
WLAN when LTE
transmitting
1.8 V
60
WLAN_TX_EN*
DI
Notification from WLAN
to SDR while
transmitting
1.8 V
61
ANTCTL1 *
DO, PD
Antenna GPIO control
1.8 V
62
COEX_RXD*
DI, PD
LTE/WLAN coexistence
receive data
1.8 V
63
ANTCTL2*
DO, PD
Antenna GPIO control
1.8 V
64
COEX_TXD*
DO, PD
LTE/WLAN coexistence
transmit
1.8 V
65
RFFE_VIO_1V8
2)
PO
Power supply for
antenna tuner
1.8 V
Maximum output
current: 50 mA
66
USIM1_DET
1)
DI, PU
(U)SIM1 card insertion
detection
1.8 V
67
RESET#
DI
Reset the module.
Active LOW
V
IH
max = 2.1 V
V
IH
min = 1.3 V
V
IL
max = 0.5 V
Internally pulled
up to 1.8 V with a
100 kΩ resistor
68
AP2SDX_STATUS*
DI
Status indication from
AP
1.8 V