Quectel 5G Series Hardware Design

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 53 / 85
4.5.6. STATUS*
RM500Q-GL provides two status indication pins for communication with IPQ807x device. Pin 38
(SDX2AP_STATUS) outputs the status indication signal to IPQ807x device, and pin 68
(AP2SDX_STATUS) inputs the status indication signal from IPQ807x device. For more details, see
document [5].
4.6. Cellular/WLAN COEX Interface*
RM500Q-GL provides a cellular/WLAN COEX interface, the following table shows the pin definition of this
interface.
Table 26: Pin Definition of COEX Interface
4.7. Antenna Tuner Control Interface*
The module provides ANTCTL[1:2] and RFFE pins used for antenna tuner control, which should be
routed to an appropriate antenna control circuit. More details about the interface will be added in the
future version of this document.
Table 27: Pin Definition of Antenna Tuner Control Interface
Pin No.
Pin Name
I/O
Description
DC Characteristic
59
LAA_TX_EN*
DO
Notification from SDR to WLAN when
LTE transmitting
1.8 V
60
WLAN_TX_EN*
DI
Notification from WLAN to SDR while
transmitting
1.8 V
62
COEX_RXD*
DI, PD
LTE/WLAN coexistence receive
1.8 V
64
COEX_TXD*
DO, PD
LTE/WLAN coexistence transmit
1.8 V
Pin No.
Pin Name
I/O
Description
DC Characteristic
56
RFFE_CLK
1)
DO, PD
Used for external RFFE
IC control
1.8 V
58
RFFE_DATA
1)
DO, PD
1.8 V

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English