Quectel 5G Series Hardware Design

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 43 / 85
1. The underlined value is the default parameter value.
2. For more details about the command, see document [4].
4.3.2. Pin Definition of PCIe
The following table shows the pin definition of PCIe interface.
Table 16: Pin Definition of PCIe Interface
Pin No.
Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AIO
PCIe reference clock (+)
100 MHz.
Require differential
impedance of 85 Ω
53
PCIE_REFCLK_M
AIO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive (+)
Require differential
impedance of 85 Ω
47
PCIE_RX_M
AI
PCIe receive (-)
43
PCIE_TX_P
AO
PCIe transmit (+)
Require differential
impedance of 85 Ω
41
PCIE_TX_M
AO
PCIe transmit (-)
50
PCIE_RST_N
DI, OD
PCIe reset.
Active LOW
52
PCIE_CLKREQ_N
DO, OD
PCIe clock request.
Active LOW
54
PCIE_WAKE_N
DO, OD
PCIe wake up
Active LOW
NOTES

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English