Quectel 5G Series Hardware Design

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 54 / 85
1)
If this function is required, please contact Quectel for more details.
4.8. Configuration Pins
RM500Q-GL provides four configuration pins, which are defined as below.
Table 28: Configuration Pins List of M.2 Specification
Table 29: Configuration Pins of the Module
65
RFFE_VIO_1V8
1)
PO
Power supply for RFFE
1.8 V
Maximum output current: 50 mA
61
ANTCTL1*
DO, PD
Antenna Control
1.8 V
63
ANTCTL2*
DO, PD
1.8 V
Config_0
(Pin 21)
Config_1
(Pin 69)
Config_2
(Pin 75)
Config_3
(Pin 1)
Module Type and
Main Host Interface
Port
Configuration
NC
GND
NC
NC
Quectel defined
2
Pin No.
Pin Name
I/O
Description
21
CONFIG_0
DO
Not connected internally
69
CONFIG_1
DO
Connected to GND internally
75
CONFIG_2
DO
Not connected internally
1
CONFIG_3
DO
Not connected internally
NOTE

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English