Quectel 5G Series Hardware Design

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 33 / 85
3.6. Reset the Module
RESET# is an asynchronous and active LOW signal (1.8 V logic level). Whenever this pin is active, the
module will immediately enter Power On Reset (POR) condition.
Please note that triggering the RESET# signal will lead to loss of all data in the modem and removal of
system drivers. It will also disconnect the modem from the network.
Table 12: Definition of RESET# Pin
The module can be reset by pulling down the RESET# pin for 200–980 ms. An open collector/drain driver
or button can be used to control the RESET# pin.
Host Module
RESET#
PMIC
GPIO
67
VDD 1.8V
Reset pulse
200-980ms
Q1
NPN
R1
100k
R3
100k
R2
1k
Figure 12: Reference Circuit of RESET# with NPN Driver Circuit
Pin No.
Pin Name
I/O
Description
DC Characteristic
Comment
67
RESET#
DI, PU
Reset the module
Active LOW
V
IH
max = 2.1 V
V
IH
min = 1.3 V
V
IL
max = 0.5 V
Internally pulled up to
1.8 V with a 100 kΩ
resistor

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English