Quectel 5G Series Hardware Design

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 34 / 85
Module
RESET#
Reset
Logic
67
VDD 1.8V
200-980 ms
S1
TVS
R1
100k
33 pF
C1
NOTE: The capacitor C1 is recommended to be less than 47 pF.
Figure 13: Reference Circuit of RESET# with Button
The reset timing is illustrated by the following figure.
VCC(H)
RESET#
Module Status
FCPO#(H)
RFFE_VIO_1V8
ResettingRunning Restarting
1.8 V
3.7 V
USIM_VDD
V
IH
≥ 1.19 V
1.8 V or 3.0 V
1.8 V
T
RST#-USIM
200 ms ≤ T
RST#
≤ 980 ms
NOTE: The host GPIO only needs to control RESET# to reset the module.
Figure 14: Reset Timing of the Module
Table 13: Reset Timing of the Module
Symbol
Min.
Typ.
Max.
Comment
T
RST#-USIM
200 ms
(U)SIM card turn-off time.
T
RST#
200 ms
400 ms
980 ms
T
RST#
≥ 980 ms will cause repeated reset.

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English