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Quectel 5G Series Hardware Design

Quectel 5G Series
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5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 4 / 85
About the Document
Revision History
Version
Date
Author
Description
1.0
2020-08-31
Norton ZHANG/
Kingson ZHANG
Qiqi WANG
Initial
1.1
2021-03-10
Norton ZHANG
Jerax KONG
1. Updated the status of 5G NR SA bands (in Table 2);
2. Added the supported GNSS system: GZSS (in Table 2);
3. Updated application fields of the module (in Chapter 2.1);
4. Updated the content and notes of key features (Chapter
2.2);
5. Updated 5G NR features (in Table 3);
6. Updated the temperature range of the module;
7. Updated I/O parameter definitions and deleted M.2 Socket
2 PCIe-based Pinout descriptions (in Chapter 2.6);
8. Updated the description of turn-on/turn-off/reset timing and
PCIe timing of the module (in Chapter 3.4, Chapter 3.5,
Chapter 3.6 and Chapter 4.3.4);
9. Updated the content of (U)SIM interfaces (Chapter 4.1);
10. Updated MIMO1 to PRX MIMO, and MIMO2 to DRX MIMO
(in Chapter 5);
11. Updated WCDMA information of ANT0 and ANT3 (in Table
30 and Table 31);
12. Updated 5G NR receiving sensitivity data (Table 33);
13. Added new chapters: Chapter 1.2, Chapter 1.3, Chapter
5.3.4, and Chapter 5.3.5;
14. Updated current consumption data (Table 40);
15. Updated the reference image of the module (Figure 38).

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Quectel 5G Series Specifications

General IconGeneral
BrandQuectel
Model5G Series
CategoryControl Unit
LanguageEnglish

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