One edge on this pin triggers a position sampling. The polarity of the edge can be pro‐
grammed using the SPOL bit in the SYS_CTRL (00h) register. The protocol requires a
constant frequency of the signal at this pin, with deviations permitted within a set toler‐
ance band. Continuously, the protocol synchronizes the protocol frame with the signal
frequency at sync.
NOTE
If the sync signal frequency is outside the tolerance range, re-synchronization of the
protocol is triggered. During the time that the re-synchronization is taking place, sam‐
pling is carried out with the former sync frequency until the re-synchronization is com‐
plete. For more details on the sync signal also see chapter 7.3.3.
5.3.2 INTERRUPT signal
interrupt is a DSL Master digital output.
interrupt is set to "1" if an interrupt condition has been fulfilled in the DSL-Master.
The interrupt conditions are set using the registers MASK_H, MASK_L and MASK_SUM
(see chapter 6.3.5 and chapter 6.3.6).
NOTE
During each write process in one of the registers EVENT_H or EVENT_L, the interrupt
output is masked until the current SPI transaction has ended.
5.3.3 LINK signal
link is a DSL Master digital output.
link is effected by the content of the LINK bit in the MASTER_QM register (see
chapter 6.3.3) and therefore indicates whether the DSL Master has produced a com‐
munications link to a connected HIPERFACE DSL
®
motor feedback system.
link is intended to be a control signal for an LED display, but can also be used to con‐
trol the start-up performance (see chapter 7.1) or for global error handling.
link is reset if communication faults are detected.
5.3.4 FAST_POS_RDY signal
fast_pos_rdy is a DSL Master digital output.
fast_pos_rdy signals that a new fast position value is available and permits an
event-based reading of the position for incorporating latency reduction.
fast_pos_rdy is always available, even if the position value is invalid or no connec‐
tion to the encoder has been established.
Dependent upon the configuration in the register system control (see chapter 6.3.1),
fast_pos_rdy displays either only the availability of positions based on user require‐
ments (edge at sync input) or all transmitted positions.
5.3.5 SYNC_LOCKED signal
sync_locked is a DSL Master digital output.
sync_locked indicates whether the sync signal was correctly passed to the encoder,
or whether the IP Core is still in a synchronization phase. sync_locked drops to “0”
when the SYNC edge supplied by the application has been transported with more than
2 clock cycles of distortion.
INTERFACES 5
8017595/ZTW6/2018-01-15 | SICK T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
25
Subject to change without notice
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