Bit 7 LINK: DSL protocol connection status
1 = Protocol connection between DSL Master and Slave was established.
0 = No connection present or connection error due to a communications error.
It should be noted that LINK is also represented at the link interface output (see
chapter 5.3).
Bit 6-4 Not implemented: Read as "0".
Bit 3-0
QM3:QM0: Quality monitoring bits
0000 to 1111: Quality monitoring value. Higher values indicate a better connection. If
the quality monitoring reaches the value "0000", a forced reset of the protocol is car‐
ried out.
6.3.4 Events
The EVENT_H/EVENT_L registers contain the messaging bits for all warning and error
modes of the DSL system.
All messaging bits are set by the DSL Master if a corresponding status is determined.
The following bit description lists the effects of warning and error conditions as well as
the reactions to errors that must be installed in the frequency inverter application.
An event bit that has been set is not reset by the DSL Master. The frequency inverter
application must delete bits that have been set.
Both edge and level-sensitive flags are present in the EVENT registers. Edge- sensitive
bits are set when the corresponding status arises. They are only set again if the corre‐
sponding status disappears and then arises once more. This is the standard action. The
level-sensitive bits set a bit as long as the corresponding status exists.
NOTE
It should be noted that all event register bits are also transferred to Online Status D
(see chapter 6.2 and chapter 7.6.2). The event bits are not static there and contain the
actual status of each individual event.
Register 04h:
High Byte events
R-0 R/C-0 X-0 X-0 R/C-0 X-0 R/C-0 R/C-0
INT SUM POS DTE PRST
Bit 7 Bit 0
Bit 7 INT: Interrupt status
This bit reflects the status of the interrupt signal (see chapter 5.3.2).
Bit 6
SUM: Remote event monitoring
1 = The DSL Slave has signaled an event and the summary mask is set accordingly (see
registers MASK_SUM and SUMMARY).
0 = All DSL Slave events are deleted.
When the SUM bit is set, an error or a warning has been transmitted from the DSL
Slave. The frequency inverter application must check the SUMMARY register (see
chapter 6.3.14) to obtain a detailed description. This bit is level sensitive.
Bit 5 SCE: Error on the Safe Channel
1 = Data consistency error on the Safe Channel.
0 = Safe Channel data was correctly transmitted.
6
REGISTER MAP
36
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice
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