Addresses Memory area
Table 9-5 continued:
E 8000H to E 9FFFH
E B000H to E FBFFH
E A000H to E AFFFH
E FC00H to E FFFFH
F 0000H to F FFFFH
System RAM:
System data, 16 bits
System data (RI/RS, timers, counters etc.),
16 bits
S flags, 8 bits, low byte in 16-bit word
(High byte not defined)
Flags, process image, 8 bits
(High byte = FFH)
I/Os, 8/16 bits
(Refer also to Chapter 8)
Sequence
The field transfer is made in descending order, i.e. it begins with the
highest address of the source area (= end address) and ends with the
lowest.
TNW, TXB and TXW
operations
The operations TNW, TXB and TXW are long-running STEP 5
operations which can only be interrupted by POWER DOWN and
QVZ.
Special features
Interruptions
by POWER DOWN
If one of the operations is interrupted by a power failure (NAU)
followed by a warm restart, the operation does not resume at the point
at which it was interrupted but from the beginning again.
Interruptions by QVZ
If a timeout (QVZ) occurs during the transfer, the operation is
interrupted and the appropriate error OB called.
The error address is the address at which an error occurred (refer to
Section 5.6.3).
Transferring Memory Blocks
CPU 948 Programming Guide
9 - 20 C79000-G8576-C848-04
To Next Page
Loading...
Need help?
General
