Siemens S7-1200 - Page 416

Technology instructions
9.1 High-speed counter
S7-1200 Programmable controller
416 System Manual, 03/2014, A5E02486680-AG
Table 9- 9 CPU 1214C, CPU 1215C, and CPU1217C:
HSC default address assignments
(on-board inputs only, see next table for optional SB addresses)
HSC counter mode
Digital input byte 0
(default: 0.x)
Digital input byte 1
(default: 1.x)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
HSC 1
1-phase
C
[d]
[R]
2-phase
CU
CD
[R]
AB-phase
A
B
[R]
HSC 2
1-phase
[R]
C
[d]
2-phase
[R]
CU
CD
AB-phase
[R]
A
B
HSC 3
1-phase
C
[d]
[R]
2-phase
CU
CD
[R]
AB-phase
A
B
[R]
HSC 4
1-phase
[R]
C
[d]
2-phase
[R]
CU
CD
AB-phase
[R]
A
B
HSC 5
1-phase
C
[d]
[R]
2-phase
CU
CD
[R]
AB-phase
A
B
[R]
HSC 6
1-phase
C
[d]
[R]
2-phase
CU
CD
[R]
AB-phase A B [R]
Table 9- 10 Optional SB in CPUs in above table: HSC default address assignments
HSC
Optional SB inputs (default: 4.x)
1
0
1
2
3
HSC 1 1-phase C [d] [R]
2-phase
CU
CD
[R]
AB-phase
A
B
[R]
HSC 2
1-phase
[R]
C
[d]
2-phase
[R]
CU
CD
AB-phase
[R]
A
B
HSC 5
1-phase
C
[d]
[R]
2-phase
CU
CD
[R]
AB-phase
A
B
[R]
HSC 6
1-phase
[R]
C
[d]
2-phase
[R]
CU
CD
AB-phase
[R]
A
B
1
An SB with only 2 digital inputs provides only the 4.0 and 4.1 inputs.