Overvoltage positive sequence system U
1
The device calculates the positive sequence system according to its defining equation
U
1
=
1
/
3
·(U
L1
+ a·U
L2
+ a
2
·U
L3
)
where a = e
j120°
.
The resulting positive sequence voltage is fed to the two threshold stages U1> (address 3732) and U1>>
(address 3734) (see Figure 2-26). Combined with the associated time delays T U1> (address 3733) and T
U1>> (address 3735), these stages form a two-stage overvoltage protection based on the positive sequence
system. Here too, the drop-out to pickup ratio can be set.
The overvoltage protection for the positive sequence system can also be blocked via a binary input
>U1>(>)
BLK
.
[logikdia-ueberspgschutz-spgmitsys-wlk-310702, 1, en_GB]
Figure 2-26
Logic diagram of the overvoltage protection for the positive sequence voltage system
Please bear in mind that the device is designed for a three-phase voltage connection. Single-phase connection
is also possible but no adjustments have been made in this respect. This must be taken into consideration
when setting the pickup value.
Overvoltage negative sequence system U
2
The device calculates the negative sequence system voltages according to its defining equation:
U
2
=
1
/
3
·(U
L1
+ a
2
·U
L2
+ a·U
L3
)
where a = e
j120°
.
The resulting negative sequence voltage is fed to the two threshold stages U2> (address 3742) and U2>>
(address 3744). Figure 2-27 shows the logic diagram. Combined with the associated time delays T U2>
(address 3743) and T U2>> (address 3745), these stages form a two-stage overvoltage protection for the
negative sequence system. Here too, the drop-out to pickup ratio can be set.
Functions
2.5 Under and over-voltage protection (optional)
SIPROTEC 4, 7VK61, Manual 99
C53000-G1176-C159-5, Edition 05.2018