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5 - Peripherals
05-SCI1
The receive mechanism is a bit more complicated. The receive clock must first be set to the
same frequency as the transmit clock of the source of the serial data to be received. Since the
start bit is used to resynchronize the clocks, the clock frequency has a fairly wide tolerance
since it is allowed to shift by a half-bit period atthe end of the transmission, that is,11 bits. This
gives a tolerance of about 5%, which is not a problem to achieve.
Baud rate
generator
f
cpu
1
stop
0
start
transmit shift register
8 or 9 bits long
Internal data bus
Data register
T8 M
1=9 bits
0=8 bits
SCICR1
TDO
TDR
Transmit
control
TDRE TC
SCISR
I
CCR
TCIE
SCICR2
SCI simplified transmit bock diagram
TCIE: Transmission complete interrupt enable
TE: assign TDO pin to alternate function
TDRE: Transmit data register empty
TC: Transmission complete
T8: to store the 9th bit when M=1
M: Word length
TE
Interrupt to
the core
TIE
Internal
write command
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