DocID15067 Rev 3 7/49
AN2834 ADC internal principle
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Figure 2. Sample state
1. Sample state: capacitors are charging to V
IN
voltage. Sa switched to V
IN
, Sb switch closed during sampling
time.
Figure 3. Hold state
1. Hold state: the input is disconnected, capacitors hold input voltage. Sb switch is open, then S1-S11
switched to ground and Sa switched to V
REF
.
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