Reference
Bottom Side Description
Level (State Input)N
Level (Clock Input) N
Sets the threshold voltage level for state and clock signals to level N,
using the general purpose knob.
Set to TTL Sets the threshold voltage level to 1.4 V for both inputs.
Set to ECL Sets the threshold voltage level to -1.3 V for both inputs.
Thresholds
Set to 50% Sets the threshold voltage level to 50% of each input's peak-to-peak
value.
Mode & Holdoff The table on Edge triggering includes a description of this menu item.
(See page
94.)
Key Points
Trigger When. The state signal must be true or false for ≥2 ns prior to the clock
transition in order for the oscilloscope to detect the state.
Pulse Triggers
Pulse Width Trigger. Pulse-width triggering triggers the oscilloscope when a
signal
pulse width is less than, greater than, equal to, or not equal to a specified
pulse width. This trigger is useful for digital logic troubleshooting.
Pulse Width Trigger Conditions
Push the Trigger Menu button, and then push the Type bottom screen button to
select Pulse. The next table lists the menu items when the trigger Type is set to
Pulse, and the Class is set to Width.
102 TDS3000C Series Oscilloscope User Manual
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