CC1101
SWRS061H Page 49 of 98
18.2 Interleaving
Data received through radio channels will
often experience burst errors due to
interference and time-varying signal strengths.
In order to increase the robustness to errors
spanning multiple bits, interleaving is used
when FEC is enabled. After de-interleaving, a
continuous span of errors in the received
stream will become single errors spread apart.
CC1101
employs matrix interleaving, which is
illustrated in Figure 24. The on-chip
interleaving and de-interleaving buffers are 4 x
4 matrices. In the transmitter, the data bits
from the rate ½ convolutional coder are written
into the rows of the matrix, whereas the bit
sequence to be transmitted is read from the
columns of the matrix. Conversely, in the
receiver, the received symbols are written into
the rows of the matrix, whereas the data
passed onto the convolutional decoder is read
from the columns of the matrix.
CC1101
employs a 4x4 matrix interleaver with 2
bits (one encoder output symbol) per cell and
the amount of data transmitted over the air will
thus always be a multiple of four bytes (see
DN507 [20] for more details). When FEC and
interleaving is used, at least one extra byte is
required for trellis termination and the packet
control hardware therefore automatically
inserts one or two extra bytes at the end of the
packet. These bytes will be invisible to the
user, as they are removed before the received
packet enters the RXFIFO.
When FEC and interleaving is used the
minimum data payload is 2 bytes.
Packet
Engine
FEC
Encoder
Modulator
Interleaver
Write buffer
Interleaver
Read buffer
Demodulator
FEC
Decoder
Packet
Engine
Interleaver
Write buffer
Interleaver
Read buffer
Figure 24: General Principle of Matrix Interleaving
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