CC1101
SWRS061H Page 63 of 98
27 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been included in the
CC1101
to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller, and
simplify software development.
27.1 Asynchronous Serial Operation
Asynchronous transfer is included in the
CC1101
for backward compatibility with systems
that are already using the asynchronous data
transfer.
When asynchronous transfer is enabled,
several of the support mechanisms for the
MCU that are included in
CC1101
will be
disabled, such as packet handling hardware,
buffering in the FIFO, and so on. The
asynchronous transfer mode does not allow
for the use of the data whitener, interleaver,
and FEC, and it is not possible to use
Manchester encoding. MSK is not supported
for asynchronous transfer.
Setting PKTCTRL0.PKT_FORMAT to 3
enables asynchronous serial mode. In TX, the
GDO0 pin is used for data input (TX data).
Data output can be on GDO0, GDO1, or
GDO2. This is set by the
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG
and IOCFG2.GDO2_CFG fields.
The
CC1101
modulator samples the level of the
asynchronous input 8 times faster than the
programmed data rate. The timing requirement
for the asynchronous stream is that the error in
the bit period must be less than one eighth of
the programmed data rate.
In asynchronous serial mode no data decision
is done on-chip and the raw data is put on the
data output line in RX. When using
asynchronous serial mode make sure the
interfacing MCU does proper oversampling
and that it can handle the jitter on the data
output line. The MCU should tolerate a jitter of
±1/8 of a bit period as the data stream is time-
discrete using 8 samples per bit.
In asynchronous serial mode there will be
glitches of 37 - 38.5 ns duration (1/XOSC)
occurring infrequently and with random
periods. A simple RC filter can be added to the
data output line between
CC1101
and the MCU
to get rid of the 37 - 38.5 ns ns glitches if
considered a problem. The filter 3 dB cut-off
frequency needs to be high enough so that the
data is not filtered and at the same time low
enough to remove the glitch. As an example,
for 2.4 kBaud data rate a 1 kohm resistor and
2.7 nF capacitor can be used. This gives a 3
dB cut-off frequency of 59 kHz.
27.2 Synchronous Serial Operation
Setting PKTCTRL0.PKT_FORMAT to 1
enables synchronous serial mode. In the
synchronous serial mode, data is transferred
on a two-wire serial interface. The
CC1101
provides a clock that is used to set up new
data on the data input line or sample data on
the data output line. Data input (TX data) is on
the GDO0 pin. This pin will automatically be
configured as an input when TX is active. The
TX latency is 8 bits. The data output pin can
be any of the GDO pins. This is set by the
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG,
and IOCFG2.GDO2_CFG fields. Time from
start of reception until data is available on the
receiver data output pin is equal to 9 bit.
Preamble and sync word insertion/detection
may or may not be active, dependent on the
sync mode set by the MDMCFG2.SYNC_MODE.
If preamble and sync word is disabled, all
other packet handler features and FEC should
also be disabled. The MCU must then handle
preamble and sync word insertion and
detection in software.
If preamble and sync word insertion/detection
are left on, all packet handling features and
FEC can be used. One exception is that the
address filtering feature is unavailable in
synchronous serial mode.
When using the packet handling features in
synchronous serial mode, the
CC1101
will insert
and detect the preamble and sync word and
the MCU will only provide/get the data
payload. This is equivalent to the
recommended FIFO operation mode.
An alternative serial RX output option is to
configure any of the GD0 pins for
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