CC1101
SWRS061H Page 36 of 98
14 Demodulator, Symbol Synchronizer, and Data Decision
CC1101
contains an advanced and highly
configurable demodulator. Channel filtering
and frequency offset compensation is
performed digitally. To generate the RSSI level
(see Section 17.3 for more information), the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
14.1 Frequency Offset Compensation
The
CC1101
has a very fine frequency
resolution (see Table 15). This feature can be
used to compensate for frequency offset and
drift.
When using 2-FSK, GFSK, 4-FSK, or MSK
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency within certain limits, by
estimating the centre of the received data. The
frequency offset compensation configuration is
controlled from the FOCCFG register. By
compensating for a large frequency offset
between the transmitter and the receiver, the
sensitivity can be improved, see DN005 [17].
The tracking range of the algorithm is
selectable as fractions of the channel
bandwidth with the FOCCFG.FOC_LIMIT
configuration register.
If the FOCCFG.FOC_BS_CS_GATE bit is set,
the offset compensator will freeze until carrier
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
the algorithm. FOCCFG.FOC_PRE_K sets the
gain before the sync word is detected, and
FOCCFG.FOC_POST_K selects the gain after
the sync word has been found.
The estimated frequency offset value is
available in the FREQEST status register. This
can be used for permanent frequency offset
compensation. By writing the value from
FREQEST into FSCTRL0.FREQOFF, the
frequency synthesizer will automatically be
adjusted according to the estimated frequency
offset. More details regarding this permanent
frequency compensation algorithm can be
found in DN015 [10].
14.2 Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 12.
Re-synchronization is performed continuously
to adjust for error in the incoming symbol rate.
14.3 Byte Synchronization
Byte synchronization is achieved by a
continuous sync word search. The sync word
is a 16 bit configurable field (can be repeated
to get a 32 bit) that is automatically inserted at
the start of the packet by the modulator in
transmit mode. The MSB in the sync word is
sent first. The demodulator uses this field to
find the byte boundaries in the stream of bits.
The sync word will also function as a system
identifier, since only packets with the correct
predefined sync word will be received if the
sync word detection in RX is enabled in
register MDMCFG2 (see Section 17.1). The
sync word detector correlates against the
user-configured 16 or 32 bit sync word. The
correlation threshold can be set to 15/16,
16/16, or 30/32 bits match. The sync word can
be further qualified using the preamble quality
indicator mechanism described below and/or a
carrier sense condition. The sync word is
configured through the SYNC1 and SYNC0
registers.
In order to make false detections of sync
words less likely, a mechanism called
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
See Section 17.2 for more details.
Note: Frequency offset compensation is
not supported for ASK or OOK modulation.
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