the contents
of
the
affected
generC'1
register(s)
after
the
instruction is successfully
completed:
Condition
code
settings:
234
o 0
Result
Zero -
the
result in
the
affected
register(s)
is
all
OIS.
- 0
Negative
-
register
R
contains
a 1 in
bit
position
O.
o Positive - register R
contains
a 0 in
bit
posi-
tion
0,
and
at
least
one
1
appears
in
the
remainder
of
the
affected
register(s) (or
appeared
duri
ng
execution
of
the
current
instruction.
)
- 0
No
fixed-point
overflow -
the
result
in
the
affected
register{s) is
arithmetically
correct.
Fixed-point
overflow -
the
result
in
the
af-
fected
register(s) is
arithmetically
incorrect.
Store instructions
affect
only
that
portion
of
memory
stor-
age
that
corresponds to the length
of
the information fie
Id
specified
by
the
operation
code
of
the
instruction;
thus,
register bytes
are
stored in memory
byte
locations,
register
halfwords in memory halfword locations,
register
words in
memory word locations, and
register
doublewords in mem-
ory doubleword locations. Store instructions do
not
affect
the
contents
of
the
general
register
specified
by
the
R
field
of
the
instruction,
unless the same register is also
specified
by
~h~
cffc~trvc
~';;i'"~uG!
Gddi'"~:;::;
~f
th~
;~:;tr:":~~:C:i.
LI
LOAD
IMMEDIATE
(Immedi
ate
operand)
o I 2
LOAD IMMEDIATE
extends
the
sign
of
the
value
field (bit
position 12
of
the instruction word) 12
bit
positions to
the
left and then loads the
32-bit
result into
register
R.
Affected:
(R),
CC3,
CC4
(I)
12
-31 S
E-
R
Condition
code settings:
2 3 4 Result in R
-
0 0 Zero
-
0
Negative
o Positive
Trap:
Nonexistent
instruction,
if
bit
0 is a 1.
If
LI
is
indirectly
addressed,
it
is
treated
as a
nonexistent
instruction,
in which case the
BP
unconditionally
aborts
execution
of
the
instruction
(at
the
time
of
operation
code
decoding)
and
traps
to
location
X
l
40
1
with
the
contents
of
register
R
and
the
condition
code
unchanged.
LB
LOAD
BYTE
(Byte
index
alignment)
o I 2
LOAD
BYTE
loads
the
effective
byte
into
bit
positions 24-31
of
register
R
and
clears
bit
positions
0-23
of
the
register
to
all
OIS.
Affected:
(R),
CC3,
CC4
EB--
R
24
-
31
;
0--R
O
_
23
Condition
code
settings:
2 3 4
Resu
I
tin
R
-
0 0 Zero
o
Nonzero
LH
LOAD HALFWORD
(Halfword
index
alignment)
o I 2
LOAD HALFWORD
extends
the
sign
of
the
effective
half-
word 16
bit
positions to
the
left
and
then
loads
the
JL-bit
result
into
register
R.
Affected:
(R),
CC3,
CC4
EHSE-R
Condition
code
settings:
2 3 4 Result in R
- 0 0
Zero
- 0
Negative
o Positive
LW
LOAD WORD
(Word
index
alignment)
LOAD WORD loads
the
effective
word
into
register
R.
Affected:
(R),
CC3,
CC4
EW--R
Load/Store
Instructions
49
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