MW
MULTIPLY
WORD
0/'Iord
index
alignment)
MULTIPLY
WORD
multiplies the contents
of
register
Rul
by the
effective
word, loads the
32
high-order
bits
of
the product into register R
and
then loads the
32
low-
order bits
of
the product into register
Rul
{overflow
cannot
occur}.
If
R is odd
value,
the result in register R is the
32
low-
order
bits
of
the product. Thus, in
order
to
generate
a
64-bit
product, the R field
of
the
instruction must be
even
and the multiplicand must be in register R+l. The
condi-
tion
code
settings
are
based on the
64-bit
product formed
during instruction
execution,
rather
than on the final
con-
tents of register
R.
Affected:
(R),
(Ru
1), CC
(Rul) x
EW-R,
Rul
Condi
ti
on
code
setti ngs:
2 3 4
64-bi
t product
-
0 0 Zero.
-
0
Negative.
o Positive.
- 0 Result
is
correct,
as represented in
regis-
ter
Ru
1.
DH
o 0 Result is not
correctly
representable in
reg-
ister Rul
alone.
DIVIDE
HALFWORD
(Halfword
index
alignment)
DIVIDE
HALFWORD
divides the contents
of
register
R
(treated as a
32-bit
fi
xed-point
integer) by the
effective
halfword and loads the
quotient
into register
R.
If the
absolute value
of
the
quotient
cannot
be
correctly
repre-
sented in
32
bits,
fixed-point
overflow occurs; in which
case
CC2 is
set
to 1 and the contents
of
register
R,
and
CC1, CC3, and CC4
are
unchanged.
Affected:
(R),
CC2, CC3,
CC4
Trap:
Fixed-pointoverflow
(R)
-:-
EH-R
Condition
code
settings:
2 3 4
Result in R
-
0 0 0 Zero
quotient,
no
overflow.
- 0 0
Negative
quotient,
no overflow.
- 0
o Positi ve quoti
ent,
no overflow.
Fixed-point
overflow.
If
CC2 is
set
to 1
and
the
fixed-point
arithmetic
trap mask
(AM)
is a 1, the
BP
traps to location X
I
43
1
with the
con-
tents
of
register
R,
CC1, CC3, and
CC4
unchanged.
DW
DIVIDE WORD
(yVord
index
alignment)
DIVIDE
WORD divides the
contents
of
registers
Rand
Ru
1
(treated as a
64-bit
fixed-point
integer)
by the
effective
word, loads the
integer
remainder into register R and then
loads the
integer
quotient
into register Rul. If a nonzero
remainder
occurs,
the remainder has the same sign as the
dividend
(original contents
of
register
R).
If R
is
an odd
value,
DW
forms a
64-bit
register
operand
by
extending
the sign
of
the
contents
of
register R
32
bit
positions to
the
left, then
divides
the
64-bit
register operand by
the
effec-
tive
word,
and
loads
the
quotient
into register
R.
In
this
case,
the remainder is lost and
only
the
contents
of
reg-
ister R
are
affected.
If
the absolute
value
of
the
quotient
cannot
be
correctly
represented in
32
bits,
fixed-point
overflow occurs; in
which case
CC2
is
set
to 1 and the
contents
of
register
R,
register Rul, CC1, CC3, and
CC4
remain unchanged;
otherwise,
CC2
is reset to 0, CC3 and
CC4
reflect
the
quoti
ent
in regi
ster
Ru
1,
and
CC 1 is
unchanged.
Affected:
(R),
(Rul), CC2
CC3,CC4
Trap:
Fixed-point
overflow
(R,
Rul)
-:-
EW-
R (remainder),
Rul
(quotient)
Condition
code
settings:
2 3 4
Resu
I
tin
Ru
1
-
0 0 0
Zero
quotient,
no overflow.
- 0 0
Negative
quotient,
no overflow.
- 0 0
Positive
quotient,
no overflow.
Fixed-point
overflow.
If
CC2
is
set
to 1
and
the
fixed-point
arithmetic
trap mask
(AM)
is
a 1, the
BP
traps to
location
X
I
43
1
with the
Fixed-Point
Arithmetic Instructions 63
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