Xerox 550 User Manual

armed state. Note that if the interrupt level is to be
modified (i. e., the CL flag is a 1), the instruction may be
delayed unti I the interrupt system is avai lab Ie.
A summary description of the action on the interrupt level
as a function of the CL and AD flag is as follows:
Bit Positions
10 (CL)
o
o
11 (AD)
o
o
Function
No effect upon interrupt level
or PDF flag
Reset PDF flag
Clear and disarm interrupt level
Clear and arm interrupt level
If the initial Word Count within the Status Stack Pointer
Doubleword is less than 28 and not equal to 0, the basic
processor traps to location X
I
4D
1
(instruction exception
trap) without loading any new status or affecting the pa-
rameters of the Status Stack Pointer Doubleword and the
TCC2 bit is set to 1.
Affected: If word count ~ 28,
(PSWs), CC,
Status Stack Pointer
Doubleword
Interrupt
System if
(1)10=1.
Traps: Instruction excep-
tion, if word count
is less than 28 and
not 0; nonexistent
instruction if
bit 0=1.
if word count = 0, (PSWs), CC, and inTerrupT
System,
if I(lOt 1.
(PSWs) and CC
ED
O
_
3
-CC;
EDS_7 - FS, FZ, FN;
ED
8
-MS;
ED
9
-MM;
ED
lO
- DM;
ED
ll
-AM;
ED
1S
_
31
- IA;
ED
32
_
3S
-WK
ED37-39 u CI, II, EI - CI, II, EI
(Note: IIU
Il
represents inclusive OR.)
ED
S6
_
S9
-
RP only if (1)8 = 1
ED
60
-RA
ED
61
-MA
Note: If the word count ~ 28, the effective doubleword
(ED) is pulled from memory stack locations (rela-
tive addresses initial TSA-24 and initial TSA+l).
If the word count=O, the ED is pulled from real
memory locations 2 and 3.
Status Stack Pointer Doubleword: (Only if initial Word
Count ~ 28)
TSA-1 -TSA until terminal TSA = initial TSA-28;
Word Count - 1 - Word Count unti I terminal Word.
Count = initial Word Count - 28 (if initial Word Count
> 32,767, bit 48 not affected); and,
Space Count + 1 - Space Count unti I terminal Space
Count = initial Space Count + 28 (if Space Count
> 32,767, then set bi t 32 to 1).
Interrupt System:
If (1)10 = 1 and (1)11 = 1, clear and arm interrupt
level.
If (1)10 = 1 and (1)11 = 0, clear and disarm interrupt
level.
EXECUTE/BRANCH INSTRUCTIONS
The following instructions can cause the basic processor to
exeCUTe inSTrucTions in an order oTher Than Thor or sequen-
tially ascending instruction addresses:
Instruction
Name Mnemonic
Execute
EXU
Branch on Conditions Set
BCS
Branch on Conditions Reset
BCR
Branch on Incrementing Register
BIR
Branch on Decrementing Register
BDR
Branch and Li nk
BAL
The EXECUTE instruction can be used to insert another in-
struction into the program sequence, and the branch in-
structions can be used to alter the program sequence, either
unconditionally or conditionally. If a branch is uncondi-
tional (or conditional and the branch condition is satisfied),
the instruction pointed to by the effective address of the
branch instruction is normally the next instruction to be
executed. If a branch is conditional and the condition
for the branch is not satisfied, the next instruction is nor-
mally taken from the next location, in ascending sequence,
after the branch instruction.
Execute/Branch Instructions 89

Xerox 550 Specifications

General

Monthly Duty Cycle	Up to 300, 000 pages
Connectivity	Ethernet, USB
Print Speed (Color)	Up to 50 ppm
Duplex Printing	Standard
Printer Type	Laser
Supported Operating Systems	Windows, macOS, Linux
Paper Size	A4, Legal, Letter