Xilinx VC709 - Page 10

10 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Chapter 1: VC709 Evaluation Board Features
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the Configuration Options, page 61 for detailed information about the mode
switch SW11.
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470
).
I/O Voltage Rails
There are 17 I/O banks available on the Virtex-7 device. Fourteen I/O banks are available
on the VC709 board, and banks 12, 16, and 18 are not used. The voltages applied to the
FPGA I/O banks used by the VC709 board are listed in Table 1-3.
X-Ref Target - Figure 1-3
Figure 1-3: SW11 Default Settings
Table 1-2: VC709 Board FPGA Configuration Modes
Configuration Mode
SW13 DIP Switch
Settings (M[2:0])
Bus Width CCLK Direction
Master BPI 010 x8, x16 Output
JTAG 101 x1 Not applicable
UG887_c1_03_083112
1
OFF Position = 0
ON Position = 1
2 3 4 5
A25
A24 M2
M1 M0
Table 1-3: I/O Voltage Rails
FPGA (U1) Bank Power Supply Rail Net Name Voltage
Bank 0 VCC1V8_FPGA 1.8V
Bank 12 NOT USED 1.8V
Bank 13 VCC1V8_FPGA 1.8V
Bank 14 VCC1V8_FPGA 1.8V
Bank 15 VCC1V8_FPGA 1.8V
Bank 16 NOT USED 1.8V
Bank 17 VCC1V8_FPGA 1.8V
Bank 18 NOT USED 1.8V
Bank 19 VCC1V8_FPGA 1.8V
Bank 31 VCC1V5_FPGA 1.5V
Bank 32 VCC1V5_FPGA 1.5V
Bank 33 VCC1V5_FPGA 1.5V
Bank 34 VCC1V8_FPGA 1.8V