26 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Chapter 1: VC709 Evaluation Board Features
System Clock (SYSCLK_P and SYSCLK_N)
[Figure 1-2, callout 5]
The VC709 board has an LVDS 200 MHz oscillator (U51) soldered onto the back side of the
board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is
named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins H19 and G18
respectively.
• Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
• PPM frequency jitter: 50 ppm
• Differential output
The LVDS termination resistor R2, located within the FPGA via matrix on the bottom of the
board, is not populated. One possible I/O standard for the FPGA design clock input is:
NET "sysclk_p" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank 38
MRCC input
NET "sysclk_n" LOC = "G18" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R2 DNP
For more details, see the Si Time SiT9102 data sheet (www.sitime.com). The system clock
circuit is shown in Figure 1-7.
Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N)
[Figure 1-2, callout 6]
The VC709 board has a programmable low-jitter 3.3V differential oscillator (U34)
connected to the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and
USER_CLOCK_N clock signal pair are connected to FPGA U1 pins AK34 and AL34
respectively. On power-up, the user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to
810 MHz through an I
2
C interface. Power cycling the VC709 board reverts the user clock to
its default frequency of 156.250 MHz.
X-Ref Target - Figure 1-7
Figure 1-7: System Clock Source
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