Xilinx VC709 - Page 86

86 www.xilinx.com VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
Appendix C: Master UCF Listing
##
NET SFP[4]_TX_P LOC = AL2 ;# MGTXTXP3_113
NET SFP[4]_TX_N LOC = AL1 ;# MGTXTXN3_113
NET SFP[3]_TX_N LOC = AM3 ;# MGTXTXN2_113
NET SFP[3]_TX_P LOC = AM4 ;# MGTXTXP2_113
NET SFP[2]_TX_P LOC = AN2 ;# MGTXTXP1_113
NET SFP[2]_TX_N LOC = AN1 ;# MGTXTXN1_113
NET SFP[1]_TX_P LOC = AP4 ;# MGTXTXP0_113
NET SFP[1]_TX_N LOC = AP3 ;# MGTXTXN0_113
##
## SFP+ Receiver Lanes
##
NET SFP[4]_RX_P LOC = AJ6 ;# MGTXRXP3_113
NET SFP[4]_RX_N LOC = AJ5 ;# MGTXRXN3_113
NET SFP[3]_RX_P LOC = AL6 ;# MGTXRXP2_113
NET SFP[3]_RX_N LOC = AL5 ;# MGTXRXN2_113
NET SFP[2]_RX_P LOC = AM8 ;# MGTXRXP1_113
NET SFP[2]_RX_N LOC = AM7 ;# MGTXRXN1_113
NET SFP[1]_RX_P LOC = AN6 ;# MGTXRXP0_113
NET SFP[1]_RX_N LOC = AN5 ;# MGTXRXN0_113
##
## SFP+ GTH reference clock inputs:
##
NET SI5324_OUT_C_P LOC = AH8 ;# MGTREFCLK0P_113
NET SI5324_OUT_C_N LOC = AH7 ;# MGTREFCLK0N_113
NET SMA_MGT_REFCLK_N LOC = AK7 ;# MGTREFCLK1N_113 SMA J25
NET SMA_MGT_REFCLK_P LOC = AK8 ;# MGTREFCLK1P_113 SMA J26
#############################################
##
## SFP+ Control & Status I/O
## Bank 17 VCCO = 1.8V
## FPGA SFP I/O: 1.8V to 3.3V level shifters
## "netname_LS" is 1.8V FPGA side
##
## PCB has 4.7K pullups to 3.3V on SFP I/O
## at SFP connector ports.
##
## 1. FPGA INPUTS:
## A. TX_FAULT ( 1 = tranmitter fault )
## B. TX_LOS ( 1 = loss of signal )
## C. MOD_DETECT ( 0 = module present )
##
## 2. FPGA OUTPUTS:
## A. TX_DISABLE ( 1 = disable TX optics )
## B. RS0 ( 1 = full BW: rate select0 )
## ( 0 = half BW )
## C. RS1 ( tied to receiver GND: rate select1 )
## Force RS1 to GND from FPGA side.
##
#############################################
NET SFP1_TX_FAULT_LS LOC = Y38 ; # Input
NET SFP1_LOS_LS LOC = Y39 ; # Input
NET SFP1_MOD_DETECT_LS LOC = AB42 ; # Input
NET SFP1_TX_DISABLE_LS_B LOC = AB41 ; # Output
NET SFP1_RS0_LS LOC = W40 ; # Output
NET SFP1_RS1_LS LOC = Y40 ; # Output