Xilinx Virtex-4 - Page 102

102 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
Using the example in Figure 4-3, all logic is now clocked on the MII interface clock outputs.
These outputs run at 25 MHz at 100 Mb/s and 2.5 MHz at 10 Mb/s, or twice as fast as the
client clock inputs. To produce the correct clock frequency on these inputs, the MII clocks
are put through a toggle flip-flop (clocked on the falling edge of the MII clock) and routed
to the client clock inputs. The client logic must also be clock enabled to achieve the correct
Figure 4-3: MII Clock Management with Clock Enable
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
PHYEMAC#RXCLK
EMAC#PHYTXD[3:0]
PHYEMAC#RXD[3:0]
EMAC#
TX Client
Logic
RX Client
Logic
IBUFG
MII_RX_CLK_#
DQ MII_RXD_#[3:0]
IBUF
OBUF
MII_TXD_#[3:0]
QD
BUFG
MII_TX_CLK_#
PHYEMAC#MIITXCLK
Q
D
QD
CE
NC
NC
QD
QD
CE
TX_ACK
Registered
BUFG
UG074_3_68_032207
GND
www.BDTIC.com/XILINX