Xilinx Virtex-4 User Manual

116 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
Figure 4-13 shows the clock management used with the RGMII interface when following
the Hewlett Packard RGMII specification v2.0. GTX_CLK must be provided to the Ethernet
MAC with a high quality 125 MHz clock that satisfies the IEEE Std 802.3-2002
requirements. The EMAC#CLIENTTXGMIIMIICLKOUT output port connects to a DCM
which in turn drives the RGMII transmitter logic in the FPGA fabric and the
CLIENTEMAC#TXGMIIMIICLKIN input port. The RGMII_TXC_# is derived from the
CLK90 output of the DCM. The DCM is used to generate 2 ns of skew required between
RGMII_TXC_# and the RGMII_TXD_# at the FPGA device pads. This delay is specified in
the Hewlett Packard RGMII Specification, v2.0 to provide setup and hold time on the
external interface.
Figure 4-13: 1 Gb/s RGMII Hewlett Packard v2.0 Clock Management
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#PHYTXD[3:0]
EMAC#
TX CLIENT
LOGIC
RX CLIENT
LOGIC
OBUF
RGMII_TXD_#[3:0]
Q
D1
PHYEMAC#MIITXCLK
ODDR
D2
EMAC#PHYTXD[7:4]
DCM
CLKFB
CLKIN
CLK0
CLK90
BUFG
Q D1
ODDR
D2
OBUF
RGMII_TXC_#
CLIENTEMAC#DCMLOCKED
NC
NC
1
0
GTX_CLK
UG074_58_040609
BUFG
PHYEMAC#RXCLK
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
Q1
Q2
D
Notes:
1) An optional IDELAY can be used to adjust setup and hold timing.
RGMII_RXC_#
IBUFG
BUFG
CLK0
CLKIN
CLKFB
DCM
RGMII_RXD_#[3:0]
IBUF
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English