Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 127
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
R
Table 4-5 translates this into maximum frame lengths at different Ethernet MAC speeds.
The situation is worse at SGMII speeds lower than 1 Gb/s because bytes are repeated
multiple times.
Using the MGT RX Elastic Buffer
The RX elastic buffer implemented in the MGT can be used reliably when:
• 10 Mb/s operation is not required. Both 1 Gb/s and 100 Mb/s operate on standard
Ethernet MAC frame sizes only.
• When the clocks are closely related (see “Closely Related Clock Sources”).
Designers are recommended to select the FPGA Logic RX elastic buffer implementation if
they have any doubts to reliable operation.
Closely Related Clock Sources
Two cases are described with closely related clocks in SGMII mode.
• Case 1
Figure 4-20 illustrates a simplified diagram of a common situation where the Ethernet
MAC in SGMII mode is interfaced to an external PHY device. A common oscillator
source is used for both the FPGA and the external PHY.
Table 4-5: Maximum Frame Sizes for FPGA Logic RX Elastic Buffers
(100 ppm Clock Tol.)
Standard Speed Maximum Frame Size
1000BASE-X 1 Gb/s only 280,000
SGMII 1 Gb/s 280,000
SGMII 100 Mb/s 28,000
SGMII 10 Mb/s 2,800
Figure 4-20: SGMII Implementation Using Shared Clock Sources
Ethernet MAC
MGT
RX
Elastic
Buffer
SGMII Link
FPGA
125 MHz - 100 ppm
Tw i sted
Copper
Pair
10BASE-T
100BASE-T
1000BASE-T
PHY
TXP/TXN
RXP/RXN
UG074_3_82_012408
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English