Xilinx Virtex-4 - Page 29

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 29
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
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Table 2-10: Mode Configuration Pins
Signal Direction Description
TIEEMAC#CONFIGVEC[73] Input
MDIO enable. Asserting this pin enables the use of MDIO in the
Ethernet MAC. See “MDIO Interface” in Chapter 3.
TIEEMAC#CONFIGVEC[72:71] — These pins determine the speed of the Ethernet MAC after reset or power-up. These
bits can be changed in the Ethernet MAC mode configuration register (Table 3-12, page 77) through the host interface
when the host interface is selected (by setting TIEEMAC#CONFIG[67] High). When TIEEMAC#CONFIG[67] is Low,
the speed of the Ethernet MAC is directly set by these two bits.
10 = 1000 Mb/s
01 = 100 Mb/s
00 =10Mb/s
11 = not applicable
TIEEMAC#CONFIGVEC[72] Input
SPEED[1]
TIEEMAC#CONFIGVEC[71] Input
SPEED[0]
TIEEMAC#CONFIGVEC[70:68] — Defines the physical interface of the Ethernet MAC. These pins are mutually
exclusive. 10/100 MII and GMII modes are enabled when TIEEMAC#CONFIGVEC[70:68] are deasserted; the RGMII,
SGMII, and 1000BASE-X modes are not set.
TIEEMAC#CONFIGVEC[70] Input
RGMII mode enable. Asserting this pin sets the Ethernet MAC in
RGMII mode.
TIEEMAC#CONFIGVEC[69] Input
SGMII mode enable. Asserting this pin sets the Ethernet MAC in
SGMII mode.
TIEEMAC#CONFIGVEC[68] Input
1000BASE-X PCS/PMA mode enable. Asserting this pin sets the
Ethernet MAC in 1000BASE-X mode.
TIEEMAC#CONFIGVEC[67] Input
Host Interface enable. Asserting this pin enables the use of the
Ethernet MAC host interface.
TIEEMAC#CONFIGVEC[66] Input
Transmit 16-bit client interface enable. When asserted, the TX
client data interface is 16 bits wide. When deasserted, the TX
client data interface is 8 bits wide.
TIEEMAC#CONFIGVEC[65] Input
Receive 16-bit client interface enable. When asserted, the RX
client data interface is 16 bits wide. When deasserted, the RX
client data interface is 8 bits wide.
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