Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 77
UG074 (v2.2) February 22, 2010
Host Interface
R
Table 3-12: Ethernet MAC Mode Configuration Register
MSB
LSB
313029282726252423222120191817161514131211109876543210
0x300
LINK
SPEED
RGMII
SGMII
GPCS
HOST
TX16
RX16
RESERVED
Bit Description Default Value R/W
[23:0] Reserved. –
[24]
Receive 16-bit Client Interface enable: When this bit is 1, the
receive data client interface is 16 bits wide. When this bit is 0, the
receive data client interface is 8 bits wide. This bit is valid only
when using 1000BASE-X PCS/PMA mode.
TIEEMAC#CONFIGVEC[65] R
[25]
Transmit 16-bit Client Interface enable: When this bit is 1, the
transmit data client interface is 16 bits wide. When this bit is 0,
the transmit data client interface is 8 bits wide. This bit is valid
only when using 1000BASE-X PCS/PMA mode.
TIEEMAC#CONFIGVEC[66] R
[26]
Host Interface enable: When this bit is 1, the host interface is
enabled. When this bit is 0, the host interface is disabled. See
"Tie-Off Pins" on page 28.
TIEEMAC#CONFIGVEC[67] R
[27]
1000BASE-X mode enable: When this bit is 1, the Ethernet MAC
is configured in 1000BASE-X mode.
TIEEMAC#CONFIGVEC[68] R
[28]
SGMII mode enable: When this bit is 1, the Ethernet MAC is
configured in SGMII mode.
TIEEMAC#CONFIGVEC[69] R
[29]
RGMII mode enable: When this bit is 1, the Ethernet MAC is
configured in RGMII mode.
TIEEMAC#CONFIGVEC[70] R
[31:30]
Speed selection: The speed of the Ethernet MAC is defined by
the following values:
10 = 1000 Mb/s
01 = 100 Mb/s
00 =10Mb/s
11 =N/A
TIEEMAC#CONFIGVEC[72:71] R/W
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English