Xilinx Virtex-4 User Manual

76 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Table 3-10: Transmitter Configuration Register
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x280
RST
JUM
FCS
TX
VLAN
HD
IFG
RESERVED
Bit Description Default Value R/W
[24:0] Reserved. –
[25]
IFG adjustment enable: When this bit is 1, the transmitter reads
the value of CLIENTEMAC#TXIFGDELAY at the start of frame
transmission and adjusts the IFG.
TIEEMAC#CONFIGVEC[54] R/W
[26]
Half-duplex mode (applicable in 10/100 Mb/s mode only):
When this bit is 1, the transmitter operates in half-duplex mode.
When this bit is 0, the transmitter operates in full-duplex mode.
TIEEMAC#CONFIGVEC[55] R/W
[27]
VLAN enable: When this bit is 1, the transmitter allows
transmission of the VLAN tagged frames.
TIEEMAC#CONFIGVEC[56] R/W
[28]
Transmit enable: When this bit is 1, the transmitter is enabled for
operation.
TIEEMAC#CONFIGVEC[57] R/W
[29]
In-band FCS enable: When this bit is 1, the Ethernet MAC
transmitter is ready for the FCS field from the client.
TIEEMAC#CONFIGVEC[58] R/W
[30]
Jumbo frame enable: When this bit is 1, the transmitter sends
frames greater than the maximum length specified in IEEE Std
802.3-2002. When this bit is 0, it only sends frames less than the
specified maximum length.
TIEEMAC#CONFIGVEC[59] R/W
[31]
Reset: When this bit is 1, the transmitter is reset. The bit
automatically reverts to 0, This reset also sets all of the
transmitter configuration registers to their default values.
TIEEMAC#CONFIGVEC[60] R/W
Table 3-11: Flow Control Configuration Register
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x2C0
RSVD
FCTX
FCRX
RESERVED
Bit Description Default Value R/W
[28:0] Reserved. –
[29]
Flow control enable (RX): When this bit is 1, the received flow
control frames inhibit transmitter operation. When this bit is 0,
the flow control frame is passed to the client.
TIEEMAC#CONFIGVEC[62] R/W
[30]
Flow control enable (TX): When this bit is 1, the
CLIENTEMAC#PAUSEREQ signal is asserted and a flow
control frame is sent from the transmitter. When this bit is 0, the
CLIENTEMAC#PAUSEREQ signal has no effect.
TIEEMAC#CONFIGVEC[61] R/W
[31] Reserved. –
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English