Xilinx Virtex-4 User Manual

78 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Table 3-13: RGMII/SGMII Configuration Register
MSB
LSB
3130292827262524232221201918171615141312111098765432 1 0
0x320
SGMII
LINK
SPEED
RESERVED
RGMII
LINK
SPEED
RGMII
HD
RGMII
Link
Bit Description Default Value R/W
[0]
RGMII link: Valid in RGMII mode configuration only. When this
bit is 1, the link is up. When this bit is 0, the link is down. This
displays the link information from PHY to Ethernet MAC,
encoded by GMII_RX_DV and GMII_RX_ER during the IFG.
0 R
[1]
RGMII half-duplex mode: Valid in RGMII mode configuration
only. This bit is 0 for half-duplex mode and 1 for full-duplex
mode. This displays the duplex information from PHY to
Ethernet MAC, encoded by GMII_RX_DV and GMII_RX_ER
during the IFG.
0 R
[3:2]
RGMII speed: Valid in RGMII mode configuration only. Link
information from PHY to Ethernet MAC as encoded by
GMII_RX_DV and GMII_RX_ER during the IFG. This 2-bit
vector is defined with the following values:
10 = 1000 Mb/s
01 = 100 Mb/s
00 = 10 Mb/s
11 =N/A
All 0sR
[29:4] Reserved –
[31:30]
SGMII speed: Valid in SGMII mode configuration only. This
displays the SGMII speed information, as received by
TX_CONFIG_REG[11:10] in the PCS/PMA register. See
Table 4-8, page 134. This 2-bit vector is defined with the
following values:
10 = 1000 Mb/s
01 = 100 Mb/s
00 = 10 Mb/s
11 =N/A
All 0sR
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English