Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 35
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
R
Table 2-16 shows the PCS/PMA signals.
EMAC#PHYSYNCACQSTATUS Output
The output from the receiver’s synchronization state machine of
IEEE Std 802.3, Clause 36.
When asserted High, the received bitstream is synchronized. The
state machine is in one of the SYNC_ACQUIRED states of IEEE
Std 802.3, figures 36-39.
When deasserted Low, no synchronization has been obtained.
EMAC#PHYTXCHARDISPMODE Output Set running disparity for current byte.
EMAC#PHYTXCHARDISPVAL Output Set running disparity value.
EMAC#PHYTXCHARISK Output K character transmitted in TXDATA.
PHYEMAC#RXBUFSTATUS[1:0] Input
Receiver Elastic Buffer Status: Bit[1] asserted indicates overflow
or underflow.
PHYEMAC#RXCHARISCOMMA Input Comma detected in RXDATA.
PHYEMAC#RXCHARISK Input
K character received or extra data bit in RXDATA. When
RXNOTINTABLE is asserted, this signal becomes the tenth bit in
RXDATA.
PHYEMAC#RXCHECKINGCRC Input Reserved - tied to GND.
PHYEMAC#RXBUFERR Input Reserved - tied to GND.
PHYEMAC#RXCOMMADET Input Reserved - tied to GND.
PHYEMAC#RXDISPERR Input Disparity error in RXDATA.
PHYEMAC#RXLOSSOFSYNC[1:0] Input Reserved - tied to GND.
PHYEMAC#RXNOTINTABLE Input Indicates non-existent 8B/10 code.
PHYEMAC#RXRUNDISP Input
Running disparity in the received serial data. When
RXNOTINTABLE is asserted in RXDATA, this signal becomes
the ninth data bit.
PHYEMAC#RXCLKCORCNT[2:0] Input Status showing the occurrence of a clock correction.
PHYEMAC#TXBUFERR Input TX buffer error (overflow or underflow).
Table 2-15: Multi-Gigabit Transceiver Connections (Cont’d)
Signal Direction Description
Table 2-16: PCS/PMA Signals
Signal Direction Description
PHYEMAC#PHYAD[4:0] Input
Physical interface address of MDIO register set for the PCS
sublayer.
PHYEMAC#SIGNALDET Input
Signal direct from PMD sublayer indicating the presence of light
detected at the optical receiver, as defined in IEEE Std 802.3,
Clause 36. If asserted High, the optical receiver has detected light.
If deasserted Low, indicates the absence of light.
If unused, this signal should be tied High for correct operation.
EMAC#CLIENTANINTERRUPT Output Interrupt upon auto-negotiation.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English