Xilinx Virtex-4 User Manual

50 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Figure 3-13 shows the timing diagram for 16-bit transmit for an even-byte case, and
Figure 3-14 shows the timing diagram for an odd-byte case.
Figure 3-13: 16-Bit Transmit Back-to-Back Transfer (Even Byte Case)
Figure 3-14: 16-Bit Transmit Back-to-Back Transfer (Odd Byte Case)
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
D(n-2), D(n-3) D(n), D(n-1) DA1, DA0 DA3, DA2 DA5, DA4
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
1st Frame IFG 2nd Frame
ug074_3_15_101004
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
D(n-1), D(n-2) DA1, DA0 DA3, DA2 DA5, DA4
0xXX, D(n)
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
1st Frame IFG 2nd Frame
ug074_3_16_101004
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English