Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 49
UG074 (v2.2) February 22, 2010
Client Interface
R
As shown in Figure 3-12, CLIENTEMAC#TXDVLDMSW denotes an odd number of bytes
in the frame. In the odd byte case, CLIENTEMAC#TXDVLDMSW is deasserted one clock
cycle earlier than the CLIENTEMAC#TXDVLD signal, after the transmission of the frame.
Otherwise, these data valid signals are the same as shown in the even byte case
(Figure 3-11).
Back-to-Back Transfers
For back-to-back transfers, both the CLIENTEMAC#TXDVLD and
CLIENTEMAC#TXDVLDMSW must be deasserted for one PHYEMAC#MIITXCLK clock
cycle (half the clock frequency of CLIENTEMAC#TXCLIENTCLKIN) after the first frame.
During the following PHYEMAC#MIITXCLK clock cycle, both CLIENTEMAC#TXDLVD
and CLIENTEMAC#TXDVLDMSW must be set High to indicate that the first two bytes of
the destination address of the second frame is ready for transmission on
CLIENTEMAC#TXD[15:0]. In 16-bit mode, this one PHYEMAC#MIITXCLK clock cycle
IFG corresponds to a 2-byte gap (versus a 1-byte gap in 8-bit mode) between frames in the
back-to-back transfer.
Figure 3-12: 16-Bit Transmit (Odd Byte Case)
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
CLIENTEMAC#TXUNDERRUN
DA SA DATA
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
CLIENTEMAC#TXDVLDMSW
CLIENTEMAC#TXFIRSTBYTE
ug074_3_14_080705
EMAC#PHYTXCHARISK
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYTXCHARDISPMODE
(SGMII or 1000BASE-X
PCS/PMA only)
EMAC#PHYTXD[7:0]
(SGMII or 1000BASE-X
PCS/PMA only)
/T/ /R/
PRE
/S/
/I1/ /I2/ /I2/ /I2/ /I2/
FCS
SFD
/I1/
/R/
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English