Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 57
UG074 (v2.2) February 22, 2010
Client Interface
R
EMACCLIENT#RXCLIENTCLKOUT as an input, the divide-by-two clock signal is
generated. See Figure 4-28, page 139 for more information.
Figure 3-22 shows the timing of a normal inbound frame transfer for the case with an even
number of bytes in the frame.
Figure 3-23 shows the timing of a normal inbound frame transfer for the case with an odd
number of bytes in the frame.
As shown in Figure 3-22 and Figure 3-23, EMAC#CLIENTRXDVLDMSW is used to denote
an odd number of bytes in the frame. The data valid signals are shown in the even byte
case (Figure 3-22). In the odd byte case (Figure 3-23), EMAC#CLIENTRXDVLDMSW is
deasserted one clock cycle earlier compared to the EMAC#CLIENTRXDVLD signal, after
the reception of the frame. EMAC#CLIENTRXD[7:0] contains the data in this odd byte
case.
Figure 3-22: 16-Bit Receive (Even Byte Case)
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
DA SA DATA
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
ug074_3_24_082007
Figure 3-23: 16-Bit Receive (Odd Byte Case)
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
DA SA DATA
EMAC#CLIENTRXDVLD MSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
u
g
074_3_25_080805
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English