Xilinx Virtex-4 User Manual

62 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Flow Control Basics
An Ethernet MAC transmits a pause control frame for the link partner to cease
transmission for a defined period of time. For example, the left Ethernet MAC of
Figure 3-28 initiates a pause request when the client FIFO (illustrated) reaches a nearly full
state.
An Ethernet MAC responds to received pause control frames by ceasing transmission of
frames for the period of time defined in the received pause control frame. For example, the
right Ethernet MAC of Figure 3-28 ceases transmission after receiving the pause control
frame transmitted by the left Ethernet MAC. In a well-designed system, the right Ethernet
MAC ceases transmission before the client FIFO of the left Ethernet MAC is overflowed.
This provides time to empty the FIFO to a safe level before normal operation resumes. It
also safe guards the system against FIFO overflow conditions and frame loss.
Figure 3-28: Requirement for Flow Control
MAC
FIFO
Client Logic
Tx
Rx
MAC
Tx
Rx
125 MHz –100 ppm
125 MHz +100 ppm
Application
ug074_3_30_080705
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English