Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 67
UG074 (v2.2) February 22, 2010
Client Interface
R
TX_STATISTICS_VECTOR (bits 28 down to 20 inclusive) are only for half-duplex mode.
When operating in full-duplex mode these bits are set to a logic 0.
Figure 3-34: Transmitter Statistics Vector Timing
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
DA SA DATA L/T
EMAC#CLIENTTXSTATSBYTEVLD
CLIENTEMAC#TXFIRSTBYTE
ug074_3_36_080805
0 1 31
EMAC#CLIENTTXSTATS
EMAC#CLIENTTXSTATSVLD
Table 3-4: Bit Definitions for the Transmitter Statistics Vector
TX_STATISTICS_VECTOR Name Description
31 PAUSE_FRAME_TRANSMITTED
Asserted if the previous frame was a pause frame
initiated by the Ethernet MAC in response to
asserting CLIENTEMAC#PAUSEREQ.
30 Reserved Undefined.
29 Reserved Returns a logic 0.
[28:25] TX_ATTEMPTS[3:0]
The number of attempts made to transmit the
previous frame. A 4-bit number where 0x0 = one
attempt; 0x
1 = two attempts, up to 0xF which
describes 16 attempts.
24 Reserved Returns a logic 0.
23 EXCESSIVE_COLLISION
Asserted if a collision is detected on each of the
last 16 attempts to transmit the previous frame.
22 LATE_COLLISION
Asserted if a late collision occurred during frame
transmission.
21 EXCESSIVE_DEFERRAL
Asserted if the previous frame was deferred for
an excessive amount of time as defined by the
maxDeferTime constant in the IEEE Std 802.3-
2002 specification.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English