Xilinx Virtex-4 User Manual

66 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
The TX_STATISTICS_VECTOR is a 32-bit wide vector and is internal in the transmit
engine. This vector is muxed out to a one-bit signal, EMAC#CLIENTTXSTATS, as shown in
Figure 3-32.
The block diagram for the transmitter statistics mux in the Ethernet MAC is shown in
Figure 3-33.
All bit fields in EMAC#CLIENTTXSTATS are only valid when the
EMAC#CLIENTTXSTATSVLD is asserted as illustrated in Figure 3-34.
EMAC#CLIENTTXSTATSBYTEVLD is asserted if an Ethernet MAC frame byte (DA to FCS
inclusive) is being transmitted. The signal is valid on every
CLIENTEMAC#TXCLIENTCLKIN cycle.
Figure 3-32: Transmitter Statistics Mux Timing
UG074_03_34_080805
012345
28 29 30 31
CLIENTEMAC#TXCLIENTCLKIN
TX_STAT ISTICS_VALID
(internal signal)
TX_STAT ISTICS_VECTOR[31:0]
(internal signal)
EMAC#CLIENTTXSTATSVLD
EMAC#CLIENTTXSTATS
Figure 3-33: Transmitter Statistics Mux Block Diagram
TX_STAT ISTICS_VALID
(Internal Signal)
TX_STAT ISTICS_VECTOR[31:0]
(Internal Signal)
Ethernet MAC Block
Ethernet MAC
TXSTAT SMUX
TXSTAT SDEMUX
User Defined
Statistics Processing Block
[31:0]
EMAC#CLIENTTXSTATSBYTEVLD
EMAC#CLIENTTXSTATS
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXCLIENTCLKIN
RESET
TXSTAT SVEC[31:0] TXSTATSVLD
EMAC#CLIENTTXSTATSVLD
FPGA Fabric
ug074_3_35_080805
CLIENTEMAC#TXCLIENTCLKIN
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English