Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 69
UG074 (v2.2) February 22, 2010
Client Interface
R
The block diagram for the receiver statistics MUX in the Ethernet MAC is shown in
Figure 3-36.
Figure 3-36: Receiver Statistics MUX Block Diagram
RX_STAT ISTICS_VECTOR[26:0]
(Internal Signal)
RX_STAT ISTICS_VALID
(Internal Signal)
Ethernet MAC
RXSTAT SMUX
RXSTAT SDEMUX
User Defined
Statistics Processing Block
[26:0]
EMAC#CLIENTRXSTATSBYTEVLD
EMAC#CLIENTRXSTATS[6:0]
CLIENTEMAC#RXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
RESET
RXSTAT SVEC[26:0] RXSTATSVLD
EMAC
#CLIENTRXSTAT SVLD
ug074_3_38_080805
Ethernet MAC Block
FPGA Fabric
CLIENTEMAC#RXCLIENTCLKIN
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English