Xilinx Virtex-4 User Manual

84 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
The DCR bridge ignores any new DCR command for host access until the current host
access is complete. Therefore, it is essential to determine when the host access is complete
before issuing a new DCR command.
Table 3-21 shows the DCR addresses for the DCRs. The user assigns the DCR address bits
[9:2] in the DCR address space. UG018
, PowerPC 405 Processor Block Reference Guide
describes the DCR operation.
The four registers and the contents of the registers are shown in Table 3-22 through
Table 3-25. DCR registers are big endian.
Table 3-21: Ethernet MAC Host Interface Device Control Register Addresses
DCR Address DCR Name Register Width R/W
**_****_1100 dataRegMSW 32 bits R/W
**_****_1101 dataRegLSW 32 bits R/W
**_****_1110 cntlReg 32 bits R/W
**_****_1111 RDYstatus 32 bits R
(1)
Notes:
1. This register is Read Only.
Table 3-22: DCR Data Register dataRegMSW
DCR
Offset
MSB
LSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0xC dataRegMSW
Bit Description Default Value
[31:0]
Data – Data input from the DCR bus for the Ethernet MAC registers is written into this
register, and the most significant word of data is read out from the Ethernet MAC registers
and deposited into this register.
Undefined
Table 3-23: DCR Data Register dataRegLSW
DCR
Offset
MSB
LSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0xD dataRegLSW
Bit Description Default Value
[0:31]
Data – Data input from the DCR bus for the Ethernet MAC registers is written into this
register, and the least significant word of data is read out from the Ethernet MAC registers
and deposited into this register.
Undefined
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English